diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2021-04-27 01:52:57 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-10 20:31:30 +0000 |
| commit | a04256f55b783716ef5933fcff59014bd41db2a8 (patch) | |
| tree | f99cdd7c0ae8428f76ffaf473bca887770adc165 /src/include/cpu | |
| parent | 206dfbf17349485e1f6d9e8351277edb673a5d24 (diff) | |
*x86: fix x2apic mode boot issue
Fix booting issues on google/kahlee introduced by CB:51723.
Update use inital apic id in smm_stub.S to support xapic mode error.
Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode.
TEST=Boot to OS and check apicid, debug log for CPUIDs
cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/x86/lapic.h | 6 | ||||
| -rw-r--r-- | src/include/cpu/x86/lapic_def.h | 2 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index e2ca297659..717fc9aa38 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -12,7 +12,7 @@ static inline bool is_x2apic_mode(void) { msr_t msr; msr = rdmsr(LAPIC_BASE_MSR); - return (msr.lo & LAPIC_BASE_MSR_X2APIC_MODE); + return ((msr.lo & LAPIC_BASE_X2APIC_ENABLED) == LAPIC_BASE_X2APIC_ENABLED); } static inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid) @@ -79,8 +79,8 @@ static inline void disable_lapic(void) static __always_inline unsigned int initial_lapicid(void) { uint32_t lapicid; - if (is_x2apic_mode()) - lapicid = lapic_read(LAPIC_ID); + if (is_x2apic_mode() && cpuid_get_max_func() >= 0xb) + lapicid = cpuid_ext(0xb, 0).edx; else lapicid = cpuid_ebx(1) >> 24; return lapicid; diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index 5b25e5a968..d5e863a26c 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -5,6 +5,8 @@ #define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8) #define LAPIC_BASE_MSR_X2APIC_MODE (1 << 10) #define LAPIC_BASE_MSR_ENABLE (1 << 11) +#define LAPIC_BASE_X2APIC_ENABLED \ + (LAPIC_BASE_MSR_X2APIC_MODE | LAPIC_BASE_MSR_ENABLE) #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 #ifndef LOCAL_APIC_ADDR |