diff options
| author | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:11:02 +0000 |
|---|---|---|
| committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:11:02 +0000 |
| commit | 577f185d382c8130f20f0ee7e8466ed8bbebbacc (patch) | |
| tree | c3f330ea32887ab26c50cc0fd774cd6f5d0b0d2d /src/include/cpu | |
| parent | fcb591ac680f2b82aacb01e63a4ab91724e1e464 (diff) | |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-29
Creator: Hamish Guthrie <hamish@prodigi.ch>
Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/amd/gx1def.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/include/cpu/amd/gx1def.h b/src/include/cpu/amd/gx1def.h new file mode 100644 index 0000000000..ee36a68578 --- /dev/null +++ b/src/include/cpu/amd/gx1def.h @@ -0,0 +1,54 @@ +/* + freebios/src/northbridge/nsc/gx1/gx1def.inc + + Copyright (c) 2002 Christer Weinigel <wingel@hack.org> + + Defines for the GX1 processor +*/ + +#define GX_BASE 0x040000000 + +/**********************************************************************/ +/* Display Controller Registers, offset from GX_BASE */ + +#define DC_UNLOCK 0x8300 +#define DC_UNLOCK_MAGIC 0x4758 + +#define DC_GENERAL_CFG 0x8304 + +/**********************************************************************/ +/* Bus Controller Registers, offset from GX_BASE */ + +#define BC_DRAM_TOP 0x8000 + +#define BC_XMAP_1 0x8004 +#define BC_XMAP_2 0x8008 +#define BC_XMAP_3 0x800c + +/**********************************************************************/ +/* Memory Controller Registers, offset from GX_BASE */ + +#define MC_MEM_CNTRL1 0x8400 +#define SDCLKSTRT (1<<17) +#define RFSHRATE (0x1ff<<8) +#define RFSHSTAG (0x3<<6) +#define X2CLKADDR (1<<5) +#define RFSHTST (1<<4) +#define XBUSARB (1<<3) +#define SMM_MAP (1<<2) +#define PROGRAM_SDRAM (1<<0) + +#define MC_MEM_CNTRL2 0x8404 +#define SDCLK_MASK 0x000003c0 +#define SDCLKOUT_MASK 0x00000400 + +#define MC_BANK_CFG 0x8408 +#define DIMM_PG_SZ 0x00000070 +#define DIMM_SZ 0x00000700 +#define DIMM_COMP_BNK 0x00001000 +#define DIMM_MOD_BNK 0x00004000 + +#define MC_SYNC_TIM1 0x840c + +#define MC_GBASE_ADD 0x8414 + |