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authorFelix Held <felix-coreboot@felixheld.de>2021-07-13 02:39:09 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 17:34:36 +0000
commit4f51c94099b5a8308c0342830e1bf52f1ac095e9 (patch)
tree1aa2a200344939e019eb30ab4f015db781944250 /src/include/cpu
parentcb457aca41bcdd77b203acbcc3546923179b3764 (diff)
include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr
This MSR isn't an architectural MSR, so it shouldn't be in the common x86 MSR definition header file. From family 17h on this register has moved to a different location. Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/amd/msr.h1
-rw-r--r--src/include/cpu/x86/msr.h1
2 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index f9d20efddb..9edea5a06b 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -18,6 +18,7 @@
#define SMM_LOCK (1 << 0)
#define NB_CFG_MSR 0xC001001f
#define FidVidStatus 0xC0010042
+#define MC0_CTL_MASK 0xC0010044
#define MC1_CTL_MASK 0xC0010045
#define MC4_CTL_MASK 0xC0010048
#define MSR_INTPEND 0xC0010055
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 51ef2e08ea..b882e2f24d 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -83,7 +83,6 @@
#define IA32_VMX_BASIC_MSR 0x480
#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
#define IA32_VMX_MISC_MSR 0x485
-#define MC0_CTL_MASK 0xC0010044
#define IA32_PM_ENABLE 0x770
#define IA32_HWP_CAPABILITIES 0x771