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authorJeremy Soller <jeremy@system76.com>2022-07-26 08:18:38 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-09-16 16:17:36 +0000
commitc5d0761dea84b28cd5993b8775a4559974cc8c04 (patch)
treecf4154e0dfb7c4baf7bff4ca80600ec87340a6e8 /src/include/cpu
parent9601b1e273accfbff816cd6e7627862166cfb472 (diff)
soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID
The Q0 stepping has a different ID than P1. Reference: CML EDS Volume 1 (Intel doc #606599) Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/intel/cpu_ids.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index bb5511f126..381f20c1ac 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -44,7 +44,8 @@
#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650
#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653
#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1 0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0 0xa0655
#define CPUID_TIGERLAKE_A0 0x806c0
#define CPUID_TIGERLAKE_B0 0x806c1
#define CPUID_TIGERLAKE_R0 0x806d1