From c5d0761dea84b28cd5993b8775a4559974cc8c04 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 26 Jul 2022 08:18:38 -0600 Subject: soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID The Q0 stepping has a different ID than P1. Reference: CML EDS Volume 1 (Intel doc #606599) Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453 Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/include/cpu/intel/cpu_ids.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/include/cpu') diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index bb5511f126..381f20c1ac 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -44,7 +44,8 @@ #define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 #define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 -#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 +#define CPUID_COMETLAKE_H_S_10_2_P1 0xa0654 +#define CPUID_COMETLAKE_H_S_10_2_Q0 0xa0655 #define CPUID_TIGERLAKE_A0 0x806c0 #define CPUID_TIGERLAKE_B0 0x806c1 #define CPUID_TIGERLAKE_R0 0x806d1 -- cgit v1.2.3