diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-09 15:56:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-11 20:51:33 +0100 |
| commit | 8cc846897132f6d6baa49118005815aefb5f560f (patch) | |
| tree | 113b69cccb4728084be3c5f83f04fe9f56db43e5 /src/include/cpu/intel | |
| parent | 3b19cbae37ab340bd530e35412800a171733fda6 (diff) | |
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
And move the corresponding #define to speedstep.h
Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2339
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/speedstep.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 86778b10d5..f4c4d7283b 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -45,6 +45,7 @@ #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 +#define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_BASE_ADDR 0xe3 @@ -104,7 +105,9 @@ typedef struct { int num_states; } sst_table_t; +#ifndef __ROMCC__ void speedstep_gen_pstates(sst_table_t *); +#endif #define SPEEDSTEP_MAX_POWER_YONAH 31000 #define SPEEDSTEP_MIN_POWER_YONAH 13100 |