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authorAlicja Michalska <ahplka19@gmail.com>2024-03-01 01:39:15 +0100
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2024-03-05 23:29:17 +0000
commit4d9549b95fe15d3cdd2cf975dfffd4760602e23b (patch)
treeb3f7b166e71fe50f3c67c7fbc9da5154172e6642 /src/include/cpu/intel
parent5015a35f48aebb22e18b526be737b4ece5759a69 (diff)
soc/intel: Add definition of D0 stepping for TigerLake Halo
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/include/cpu/intel')
-rw-r--r--src/include/cpu/intel/cpu_ids.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index d74cf1e2b1..ddb4e54c1e 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -46,6 +46,7 @@
#define CPUID_COMETLAKE_H_S_10_2_Q0 0xa0655
#define CPUID_TIGERLAKE_A0 0x806c0
#define CPUID_TIGERLAKE_B0 0x806c1
+#define CPUID_TIGERLAKE_P0 0x806d0
#define CPUID_TIGERLAKE_R0 0x806d1
#define CPUID_SAPPHIRERAPIDS_SP_A 0x806f0
#define CPUID_SAPPHIRERAPIDS_SP_B 0x806f1