From 4d9549b95fe15d3cdd2cf975dfffd4760602e23b Mon Sep 17 00:00:00 2001 From: Alicja Michalska Date: Fri, 1 Mar 2024 01:39:15 +0100 Subject: soc/intel: Add definition of D0 stepping for TigerLake Halo Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/include/cpu/intel/cpu_ids.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/include/cpu/intel') diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index d74cf1e2b1..ddb4e54c1e 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -46,6 +46,7 @@ #define CPUID_COMETLAKE_H_S_10_2_Q0 0xa0655 #define CPUID_TIGERLAKE_A0 0x806c0 #define CPUID_TIGERLAKE_B0 0x806c1 +#define CPUID_TIGERLAKE_P0 0x806d0 #define CPUID_TIGERLAKE_R0 0x806d1 #define CPUID_SAPPHIRERAPIDS_SP_A 0x806f0 #define CPUID_SAPPHIRERAPIDS_SP_B 0x806f1 -- cgit v1.2.3