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| author | Ren Kuo <ren.kuo@quanta.corp-partner.google.com> | 2024-09-10 12:30:46 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-11 15:15:35 +0000 |
| commit | 5e8b7963538bf125e5b743e7a9a1e995ef6298c6 (patch) | |
| tree | ae55d2cdb42b997c5a05126007bdb346d6ea3545 /src/include/cpu/intel/microcode.h | |
| parent | 337b6f394f39470c82b0703e82d1536d9541e20d (diff) | |
mb/google/brox/var/jubilant: Enable ASPM for PCIe4 SSD of CPU
Enable ASPM of CPU PCIe4 for SSD to improve power consumption.
BUG=b:364441213
BRANCH=None
TEST="sh -c 'lspci -vvnn || lspci -nn'"
01:00.0 Non-Volatile memory controller
LnkCtl: ASPM L1 Enabled
Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/include/cpu/intel/microcode.h')
0 files changed, 0 insertions, 0 deletions