diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-06-07 11:34:28 -0400 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2022-06-09 18:06:05 +0000 |
| commit | 8d2bfbce23f6ff53cd8014286645a408886549a1 (patch) | |
| tree | b47f26d78b1ddb1ad067eff8232e12aac8339d92 /src/include/cpu/amd/msr.h | |
| parent | ba08c4904da084aac5042de6c22f7792d7023b10 (diff) | |
soc/amd/sabrina/acpi: Correct VID decoding on Sabrina
Sabrina uses the SVI3 spec for VID tables which is incompatible with the
SVI2 spec used on PCO/CZN. Move the defines from common to soc and
update the decoding for sabrina.
See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables
TEST=timeless builds on mandolin/majolica for PCO/CZN
build chausie and verify pstate power is correct in ACPI tables
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I915e962f11615246690c6be1bee3533336a808f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/include/cpu/amd/msr.h')
| -rw-r--r-- | src/include/cpu/amd/msr.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 37372d1662..76e6a8d665 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -44,9 +44,6 @@ #define PSTATE_2_MSR 0xC0010066 #define PSTATE_3_MSR 0xC0010067 #define PSTATE_4_MSR 0xC0010068 -/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_MAX_MICROVOLTS 1550000L #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 |