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authorFelix Held <felix-coreboot@felixheld.de>2023-03-10 00:04:46 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-23 23:07:51 +0000
commita25117d83f2929c4c51ec8afa0798f015cdaa3db (patch)
treed0098e5e9a7b8be28a17907656bf92e0f26e1903 /src/include/bootstate.h
parentf0b6255446a44f902da88b0f137652753d831fa4 (diff)
soc/amd/glinda: introduce and use pstate_msr bitfield struct
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs which will be implemented in a following patch. PPR #57254 Rev 1.52 was used as a reference. This patch adds and uses the cpu_vid_8 bit which is the 9th bit of the voltage ID specified in the SVI3 spec. The way the CPU frequency is encoded in the PSTATE MSR has changed compared to Phoenix, so also update the comment in the SoC's Kconfig file that the selected SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H is likely incompatible which will be addressed in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d1878ce4d9bc62ac597e6f71ef9630491628698 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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