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authorderek.huang <derek.huang@intel.corp-partner.google.com>2020-05-04 18:09:36 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-06-03 01:30:25 +0000
commitbebb2a1705b697fccf91a0f2c3a9d5870a27e9fa (patch)
tree8e036c5760647cd920123cfe2a16aecc83605416 /src/ec
parent5f86b0b7e3153240cfee3dbaade0428c8055ba5b (diff)
soc/intel/tigerlake: update elog to include CSME reset causes
Call out the CSME-initiated bits from HPR_CAUSE0 register and update the elog to include reset causes Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14 Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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