diff options
author | Sean Rhodes <sean@starlabs.systems> | 2022-03-22 10:40:51 +0000 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 16:21:31 +0000 |
commit | 36b6e79f1c482f9a02a345cfd0a76f871c015e80 (patch) | |
tree | e694a08a2abb133e4c55f7233e5777dc96016689 /src/ec/starlabs/merlin/variants | |
parent | e8b090c50917be7d5ba25d1adff799cda300ae3e (diff) |
ec/starlabs/merlin: Add EC related files for Cezanne boards
Add EC memory layout and Q events for AMD Cezanne based boards, "Byte"
and "Fighter", which both use the ITE 5570E.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/starlabs/merlin/variants')
-rw-r--r-- | src/ec/starlabs/merlin/variants/cezanne/ecdefs.h | 23 | ||||
-rw-r--r-- | src/ec/starlabs/merlin/variants/cezanne/emem.asl | 147 | ||||
-rw-r--r-- | src/ec/starlabs/merlin/variants/cezanne/events.asl | 193 |
3 files changed, 363 insertions, 0 deletions
diff --git a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h new file mode 100644 index 0000000000..a75720e34e --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE Embedded Controller + */ + +#ifndef _EC_STARLABS_CEZANNE_EC_DEFS_H +#define _EC_STARLABS_CEZANNE_EC_DEFS_H + +/* IT5570 chip ID byte values */ +#define ITE_CHIPID_VAL 0x5570 + +/* EC RAM offsets */ +#define ECRAM_KBL_BRIGHTNESS 0x09 +#define ECRAM_KBL_TIMEOUT 0x10 +#define ECRAM_KBL_STATE 0x19 +#define ECRAM_TRACKPAD_STATE 0x20 +#define ECRAM_FN_LOCK_STATE 0x21 +#define ECRAM_FN_CTRL_REVERSE 0x22 +#define ECRAM_MAX_CHARGE 0x23 +#define ECRAM_FAN_MODE 0x24 + +#endif diff --git a/src/ec/starlabs/merlin/variants/cezanne/emem.asl b/src/ec/starlabs/merlin/variants/cezanne/emem.asl new file mode 100644 index 0000000000..41d650fb36 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cezanne/emem.asl @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + OSFG, 8, // OS Flag + FRMF, 8, // Force Mirror Flag + + Offset(0x0c), + P0MV, 8, // PD Port 0 Major Version + P0SV, 8, // PD Port 0 Minor Version + P1MV, 8, // PD Port 1 Major Version + P1SV, 8, // PD Port 1 Minor Version + + Offset(0x13), + AUDI, 8, // Control Audio + TRAC, 8, // Trackpad Control + + Offset(0x18), + BSEC, 8, // Save to CMOS + KLSE, 8, // Keyboard Backlight State + TPLE, 8, // Trackpad State + FLKE, 8, // Function Lock State + FCLS, 8, // Ctrl Fn Reverse (Make Keyboard Apple-like) + MXCH, 8, // Max Charge Level + FANM, 8, // Fan Mode + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + + Offset(0x46), + ECPS, 8, // AC & Battery Status + + Offset(0x30), + STEF, 8, // Sensor T Error F + + Offset(0x62), + SSKT, 8, // System Skin Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + CHAR, 8, // Charger Temperature + + Offset(0x7f), + LSTE, 8, // Lid Status + ECPS, 8, // AC & Battery Status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining Percentage + CPUT, 8, // PECI CPU Temperature + STCD, 8, // Shutdown Code + B1HL, 8, // Battery Health + CWFU, 8, // CW2015 Full + B1CC, 16, // Battery Cycle Count + + Offset(0xb0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xc0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xd0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xe0), + CCS1, 8, // Cross Point Switch Status 1 + CCS2, 8, // Cross Point Switch Status 2 + TCI1, 8, // TC Input 1 / TCHC Thermal Charge CMD [TODO, Confirm] + TCI2, 8, // TC Input 2 / TCHF Thermal Charge Flag [TODO, Confirm] + PDDT, 8, // PD Det [TODO, Confirm] + PDBD, 8, // B PD Det [TODO, Confirm] + ECWD, 16, // EC Wakeup Delay + ECWE, 8, // EC Wakeup Enable + PDV1, 8, // PD Vol [TODO, Confirm] + PDV2, 8, // B PD Vol [TODO, Confirm] + + // Below are the Thunderbolt Offsets from the shared EC code. There aren't + // use for AMD boards but left for reference. + // + // Offset(0xf7), + // TBTC, 8, // Thunderbolt Command + // TBTP, 8, // Thunderbolt Data Port + // TBTD, 8, // Thunderbolt Data + // TBTA, 8, // Thunderbolt Acknowledge + // TBTG, 16, // Thunderbolt DBG Data +} diff --git a/src/ec/starlabs/merlin/variants/cezanne/events.asl b/src/ec/starlabs/merlin/variants/cezanne/events.asl new file mode 100644 index 0000000000..12fdf7c759 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cezanne/events.asl @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q01, 0, NotSerialized) // Event: F1 Hot Key +{ + Printf ("EC: F1") +} + +Method (_Q02, 0, NotSerialized) // Event: F2 Hot Key +{ + Printf ("EC: F2") +} + +Method (_Q03, 0, NotSerialized) // Event: F3 Hot Key +{ + Printf ("EC: F3") +} + +Method (_Q04, 0, NotSerialized) // Event: F4 Hot Key +{ + Printf ("EC: F4") +} + +Method (_Q05, 0, NotSerialized) // Event: F5 Hot Key +{ + Printf ("EC: F5") +} + +Method (_Q06, 0, NotSerialized) // Event: F6 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q07, 0, NotSerialized) // Event: F7 Hot Key +{ + Printf ("EC: F7") +} + +Method (_Q08, 0, NotSerialized) // Event: F8 Hot Key +{ + Printf ("EC: F8") +} + +Method (_Q09, 0, NotSerialized) // Event: F9 Hot Key +{ + Printf ("EC: F9") +} + +Method (_Q10, 0, NotSerialized) // Event: F10 Hot Key +{ + Printf ("EC: F10") +} + +Method (_Q12, 0, NotSerialized) // Event: F12 Hot Key +{ + Printf ("EC: F12") +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0D, 0, NotSerialized) // Event: Lid Open +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0E, 0, NotSerialized) // Event: SLEEP +{ + Printf ("EC: SLEEP") +} + +Method (_Q13, 0, NotSerialized) // Event: BRIGHTNESS +{ + Printf ("EC: BRIGHTNESS") +} + +Method (_Q20, 0, NotSerialized) // Event: CPU_T +{ + Printf ("EC: CPU_T") +} + +Method (_Q21, 0, NotSerialized) // Event: SKIN_T +{ + Printf ("EC: SKIN_T") +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q30, 0, NotSerialized) // Event: THROT_OFF +{ + Printf ("EC: THROT_OFF") +} + +Method (_Q31, 0, NotSerialized) // Event: THROT_LV1 +{ + Printf ("EC: THROT_LV1") +} + +Method (_Q32, 0, NotSerialized) // Event: THROT_LV2 +{ + Printf ("EC: THROT_LV2") +} + +Method (_Q33, 0, NotSerialized) // Event: THROT_LV3 +{ + Printf ("EC: THROT_LV3") +} + +Method (_Q34, 0, NotSerialized) // Event: THROT_LV4 +{ + Printf ("EC: THROT_LV4") +} + +Method (_Q35, 0, NotSerialized) // Event: THROT_LV5 + Printf ("EC: THROT_LV5") +} + +Method (_Q36, 0, NotSerialized) // Event: THROT_LV6 +{ + Printf ("EC:THROT_LV6") +} + +Method (_Q37, 0, NotSerialized) // Event: THROT_LV7 +{ + Printf ("EC: THROT_LV7") +} + +Method (_Q3B, 0, NotSerialized) // Event: CPU_DN_SPEED + Printf ("EC: CPU_DN_SPEED") +} + +Method (_Q3C, 0, NotSerialized) // Event: CPU_UP_SPEED +{ + Printf ("EC: CPU_UP_SPEED") +} + +Method (_Q3D, 0, NotSerialized) // Event: CPU_TURBO_OFF +{ + Printf ("EC: CPU_TURBO_OFF") +} + +Method (_Q3E, 0, NotSerialized) // Event: CPU_TURBO_ON +{ + Printf ("EC: CPU_TURBO_ON") +} + +Method (_Q3F, 0, NotSerialized) // Event: SHUTDOWN + Printf ("EC: SHUTDOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +} + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC:VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q85, 0, NotSerialized) // Event: HOME +{ + Printf ("EC: HOME") +} |