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author | Subrata Banik <subratabanik@google.com> | 2024-02-20 20:18:10 +0530 |
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committer | Subrata Banik <subratabanik@google.com> | 2024-02-25 03:56:52 +0000 |
commit | 313fdb28ca6b6479c3305d8a385389de0b2290dd (patch) | |
tree | f4596187d230fecbaf825315f76c4d2bfaa3bbe8 /src/ec/purism/librem/acpi | |
parent | 4bbace87aa6c239cbfea7703daaa0135467109cc (diff) |
mb/google/rex/var/ovis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/ovis using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/ec/purism/librem/acpi')
0 files changed, 0 insertions, 0 deletions