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authorDtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>2023-04-11 13:44:10 +0800
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2023-04-12 13:24:42 +0000
commit7e07ab95c71dd4b8a81d003bcdbdaa91fb0b3d01 (patch)
treefb5491eb1026368fd701cb8467de8ec6ac29ee2d /src/ec/google/wilco/commands.h
parent1ce9075f8cae9070bf4228374f2535950d07f00d (diff)
mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSx
This patch configures external V1p05/Vnn/VnnSx rails for Uldren to follow best practices for power savings – untested though. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74335 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/google/wilco/commands.h')
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