summaryrefslogtreecommitdiff
path: root/src/ec/google/chromeec
diff options
context:
space:
mode:
authorAndrey Petrov <andrey.petrov@intel.com>2016-04-18 13:36:19 -0700
committerAaron Durbin <adurbin@chromium.org>2016-04-28 05:11:23 +0200
commit4520c5e757cf280b7029a99adff60baed52493ce (patch)
tree0c0add2e4dfeb6c1605e98965c11fb965c92c464 /src/ec/google/chromeec
parent1ba068550d70549580838ba675c8a6543c1d175d (diff)
soc/intel/apollolake: Configure a GPIO for TPM in bootblock
One of devices connected to FAST SPI bus is TPM. SoC uses dedicated line for chip select for TPM function. If TPM is used, that line needs to be configured to a specific native funciton. Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/ec/google/chromeec')
0 files changed, 0 insertions, 0 deletions