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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-14 20:08:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-11 11:04:36 +0000 |
| commit | 663c57731185dcd25436f9ba8ebf4550d6ad4ae7 (patch) | |
| tree | db963c40a19274ef763c31a61012e0f87f091813 /src/ec/google/chromeec/smm.h | |
| parent | 543c1ee31497f97337e6e955334fc08da673b6e8 (diff) | |
soc/amd/genoa: Add USB configuration
Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.
Add USB OC pins to chipset.cb
In the process of scrubbing opensil for public release USB became non
functional.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/ec/google/chromeec/smm.h')
0 files changed, 0 insertions, 0 deletions