diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-12-07 15:55:10 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-14 16:12:43 +0000 |
| commit | abeb688154d9be5487403a65a74c8c24d380b3bf (patch) | |
| tree | 87e71fc492f4ceef9f5d2cb4fdb6cf28a50ca17b /src/ec/google/chromeec/i2c_tunnel/Kconfig | |
| parent | 20c8aa71d140d682f343892b2526001e7f528d49 (diff) | |
soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BP
The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob
and CSE RW boot are different.
TEST=Verified on drawcia.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/google/chromeec/i2c_tunnel/Kconfig')
0 files changed, 0 insertions, 0 deletions