diff options
| author | Emil Lundmark <lndmrk@chromium.org> | 2018-05-22 19:31:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-24 09:24:18 +0000 |
| commit | 9d5f9f2671aa0a27039b0cde674701bcadfa71eb (patch) | |
| tree | bb05277f5febb59f7d123949a2503f70557ee069 /src/ec/google/chromeec/acpi | |
| parent | 5eec229d9686b78abca45415f023283f9e16004c (diff) | |
chromeec: Add support for controlling USB port power
This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be
used to control the power state of up to 8 individual USB ports. Some
Chromeboxes have their GPIO pins for controlling USB port power wired to
the EC, so they cannot be accessed directly by coreboot.
Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/ec/google/chromeec/acpi')
| -rw-r--r-- | src/ec/google/chromeec/acpi/ec.asl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index ac4ceb16c5..dc0f60903e 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -91,6 +91,7 @@ Device (EC0) Offset (0x0e), Offset (0x12), BTID, 8, // Battery index that host wants to read + USPP, 8, // USB Port Power } #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) @@ -512,6 +513,26 @@ Device (EC0) Return (^TBMD) } +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER) + /* + * Enable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPS, 1, Serialized) + { + Or (USPP, ShiftLeft (1, Arg0), USPP) + } + + /* + * Disable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPC, 1, Serialized) + { + And (USPP, Not (ShiftLeft (1, Arg0)), USPP) + } +#endif + #include "ac.asl" #include "battery.asl" #include "cros_ec.asl" |