From 9d5f9f2671aa0a27039b0cde674701bcadfa71eb Mon Sep 17 00:00:00 2001 From: Emil Lundmark Date: Tue, 22 May 2018 19:31:37 +0200 Subject: chromeec: Add support for controlling USB port power This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be used to control the power state of up to 8 individual USB ports. Some Chromeboxes have their GPIO pins for controlling USB port power wired to the EC, so they cannot be accessed directly by coreboot. Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8 Signed-off-by: Emil Lundmark Reviewed-on: https://review.coreboot.org/26471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/ec/google/chromeec/acpi/ec.asl | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/ec/google/chromeec/acpi') diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index ac4ceb16c5..dc0f60903e 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -91,6 +91,7 @@ Device (EC0) Offset (0x0e), Offset (0x12), BTID, 8, // Battery index that host wants to read + USPP, 8, // USB Port Power } #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) @@ -512,6 +513,26 @@ Device (EC0) Return (^TBMD) } +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER) + /* + * Enable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPS, 1, Serialized) + { + Or (USPP, ShiftLeft (1, Arg0), USPP) + } + + /* + * Disable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPC, 1, Serialized) + { + And (USPP, Not (ShiftLeft (1, Arg0)), USPP) + } +#endif + #include "ac.asl" #include "battery.asl" #include "cros_ec.asl" -- cgit v1.2.3