diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-01-22 16:52:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-18 14:59:17 +0000 |
| commit | eb3cd856106dae68da4aae39f9954fb90770e8a2 (patch) | |
| tree | c824581892f358406184f02f355ad20c9adf6b1b /src/ec/google/chromeec/Makefile.inc | |
| parent | 214fb9b511faaa59716a1b65a43438781f6237ef (diff) | |
ec/google/chromeec: Add SSDT generator for ChromeOS EC
Upcoming patches for the Linux kernel (5.6 ?) would like to consume
information about the USB PD ports that are attached to the device. This
information is obtained from the CrOS EC and exposed in the SSDT ACPI
table.
Also, the device enable for this PCI device is moved from ec_lpc.c to
a new file, ec_chip.c, where EC-related ACPI methods can live. It
still allows other code to call functions on device enable (so that
PnP enable for the LPC device still gets called).
BUG=b:146506369
BRANCH=none
TEST=Verify the SSDT contains the expected information
Change-Id: I729caecd64d9320fb02c0404c8315122f010970b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/ec/google/chromeec/Makefile.inc')
| -rw-r--r-- | src/ec/google/chromeec/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index f2e0034bc2..4994480baa 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -24,6 +24,7 @@ verstage-y += ec.c crosec_proto.c vstore.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c ramstage-$(CONFIG_VBOOT) += vboot_storage.c smm-$(CONFIG_VBOOT) += vboot_storage.c |