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author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-04-07 20:10:05 -0500 |
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committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2023-04-10 16:41:26 +0000 |
commit | f2e8865d76107dff6113a637a232fc4cf0720be8 (patch) | |
tree | 2bc63286fab75ed2be48f82271f10a225072e006 /src/ec/compal | |
parent | 0d5b0248eb6117dc7c9ce1a7289c28f7599cdd28 (diff) |
soc/amd/common/blk/pcie: Program LTR max latencies
PCIe bridges need to provide the LTR (latency tolerance reporting)
maximum snoop/non-snoop values so that they are inherited by downstream
PCIe devices which support and enable LTR. Without this, downstream
devices cannot have LTR enabled, which is a requirement for supporting
PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior,
including some devices refusing to enter L1 low power modes at all.
Program the max snoop/non-snoop latency values for all PCIe bridges
using the same value used by AGESA/FSP, 1.049ms.
BUG=b:265890321
TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure
LTR is enabled, latency values are correctly set, and that device
power draw at idle is in the expected range (<25 mW).
Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74288
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/ec/compal')
0 files changed, 0 insertions, 0 deletions