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authorSubrata Banik <subratabanik@google.com>2024-02-20 20:18:43 +0530
committerSubrata Banik <subratabanik@google.com>2024-02-25 03:56:59 +0000
commit9305ccada13986d21ffaf874507f2d811d1ebe7b (patch)
tree0f9bf9d663fbbed1c895d73593d36973196a53c5 /src/ec/apple/acpi
parent313fdb28ca6b6479c3305d8a385389de0b2290dd (diff)
mb/google/rex/var/karis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) | v ramstage (A19/1, A20/1) Ideally, we don't need SSD power sequencing at ramstage, but due to the fact that Karis has RO locked, any change in the bootblock won't be applicable for FSI'ed karis devices. Therefore, we're keeping the existing ramstage power sequencing flow as is TEST=Able to build and boot google/karis using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80663 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/apple/acpi')
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