{commonlib/drivers}: Have option to store MRC version inside CBMEM

This patch introduces CBMEM ID to store the MRC version (similar to
existing implementation that stores the FSP-M version inside CBMEM ID)
inside cbmem so the version information is available across the
different coreboot stages. For example:

* romstage: Use the CBMEM ID version information to check if the MRC
            cache is valid and need to erase the MRC cache
* ramstage: Use the CBMEM ID to store the MRC cache into the
            non-volatile space.

BUG=b:261689642
TEST=Able to build and boot google/rex and dump the MRC version as
below.

  cbmem --list
  CBMEM table of contents:
      NAME                  ID        START     LENGTH
      ...
      21. MRC VERSION       5f43524d  75ffeb60  00000004
      ...

  localhost ~ # cbmem -r 5f43524d | hexdump
  00000000  01 12 07 00

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I91f735239b33c6f8ba41c076048903e4b213c6a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75921
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 26 insertions, 11 deletions

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index fa24a7e018..28e4d721ce 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -30,10 +30,28 @@
 
 static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
 
+/*
+ * Helper function to store the MRC cache version into CBMEM
+ *
+ * ramstage uses either the MRC version or FSP-M version (depending on the config)
+ * when updating the MRC cache
+ */
+static void do_cbmem_version_entry(uint32_t cbmem_id, uint32_t version)
+{
+	uint32_t *cbmem_version_entry = cbmem_add(cbmem_id, sizeof(version));
+	if (!cbmem_version_entry) {
+		printk(BIOS_ERR, "Failed to add %s version to cbmem.\n",
+				CONFIG(MRC_CACHE_USING_MRC_VERSION) ? "MRC" : "FSP-M");
+		return;
+	}
+	*cbmem_version_entry = version;
+}
+
 static void do_fsp_post_memory_init(bool s3wake, uint32_t version)
 {
 	struct range_entry fsp_mem;
-	uint32_t *fsp_version_cbmem;
+	uint32_t cbmem_id = CONFIG(MRC_CACHE_USING_MRC_VERSION) ? CBMEM_ID_MRC_VERSION :
+					 CBMEM_ID_FSPM_VERSION;
 
 	fsp_find_reserved_memory(&fsp_mem);
 
@@ -56,14 +74,8 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t version)
 		(uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
 		die("Failed to accommodate FSP reserved memory request!\n");
 
-	/* ramstage uses the FSP-M version when updating the MRC cache */
-	if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake) {
-		fsp_version_cbmem = cbmem_add(CBMEM_ID_FSPM_VERSION,
-					      sizeof(version));
-		if (!fsp_version_cbmem)
-			printk(BIOS_ERR, "Failed to add FSP-M version to cbmem.\n");
-		*fsp_version_cbmem = version;
-	}
+	if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake)
+		do_cbmem_version_entry(cbmem_id, version);
 
 	/* Create romstage handof information */
 	romstage_handoff_init(s3wake);
diff --git a/src/drivers/intel/fsp2_0/save_mrc_data.c b/src/drivers/intel/fsp2_0/save_mrc_data.c
index d1249424c9..19e8a52cff 100644
--- a/src/drivers/intel/fsp2_0/save_mrc_data.c
+++ b/src/drivers/intel/fsp2_0/save_mrc_data.c
@@ -11,14 +11,17 @@ static void save_mrc_data(void *unused)
 {
 	size_t mrc_data_size;
 	const void *mrc_data;
+	uint32_t cbmem_id = CONFIG(MRC_CACHE_USING_MRC_VERSION) ? CBMEM_ID_MRC_VERSION :
+					 CBMEM_ID_FSPM_VERSION;
 	uint32_t *version;
 
 	if (acpi_is_wakeup_s3())
 		return;
 
-	version = cbmem_find(CBMEM_ID_FSPM_VERSION);
+	version = cbmem_find(cbmem_id);
 	if (!version) {
-		printk(BIOS_ERR, "Failed to read FSP-M version from cbmem.\n");
+		printk(BIOS_ERR, "Failed to read %s version from cbmem.\n",
+				CONFIG(MRC_CACHE_USING_MRC_VERSION) ? "MRC" : "FSP-M");
 		return;
 	}