diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-11-20 16:47:38 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-07 11:02:03 +0000 |
| commit | 7522a8fe0f7ef91bb3e66d3df1a2786bd4744f9b (patch) | |
| tree | 6365f601165cea08a762561530643b80faf3fe81 /src/drivers | |
| parent | ca965496ffd84d8510961c520aff22bf1cc3a3eb (diff) | |
arch/x86: Move prologue to .init section
For arch/x86 the realmode part has to be located within the same 64
KiB as the reset vector. Some older intel platforms also require 4 KiB
alignment for _start16bit.
To enforce the above, and to separate required parts of .text without
matching *(.text.*) rules in linker scripts, tag the pre-C environment
assembly code with section .init directive.
Description of .init section for ELF:
This section holds executable instructions that contribute to the
process initialization code. When a program starts to run, the
system arranges to execute the code in this section before calling the
main program entry point (called main for C programs).
Change-Id: If32518b1c19d08935727330314904b52a246af3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/amd/agesa/cache_as_ram.S | 7 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.S | 2 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29b3c..33940cb489 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -10,16 +10,19 @@ ****************************************************************************** */ -#include "gcccar.inc" #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> +.section .init + .code32 -.globl _cache_as_ram_setup, _cache_as_ram_setup_end + .global bootblock_pre_c_entry _cache_as_ram_setup: +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index f1cfff771c..e20d5277ed 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -14,6 +14,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: /* |