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authorRavi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>2022-10-12 00:05:41 -0700
committerSridhar Siricilla <sridhar.siricilla@intel.com>2023-05-11 08:18:39 +0000
commit31e0aeb74778a836636573952a40c847686ef69d (patch)
treee5eded36fafad1afc820774a75e3cd82ed7df44d /src/drivers
parentd4a7dceaa589d2be44a13fc5e188ec523b1618a7 (diff)
soc/intel/meteorlake: Increase pcie snoop/non-snoop latency
This fixes an issue where pcie was not power gating and blocked S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance values to 15.73ms as stated in doc #729123 - MTL External Design Specification. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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