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authorCliff Huang <cliff.huang@intel.corp-partner.google.com>2022-04-28 18:20:27 -0700
committerFelix Held <felix-coreboot@felixheld.de>2022-06-09 13:40:08 +0000
commit0d590b7d915f47c2102b2515aca8b608205c4258 (patch)
tree90028ccf76aac457885332d1878c47c94ace4970 /src/drivers/usb/hub/acpi.c
parent61a442ec01b1a7d9a2d83604956f8355ea391b3e (diff)
soc/intel/alderlake: add support for external source clock
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9. This allows boards to use source clock 7, 8, 9. BUG=b:233252409 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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