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authorMichael Niewöhner <foss@mniewoehner.de>2020-12-21 17:09:08 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-21 18:12:25 +0000
commit17721be11a64b82d1d2bb4165bd3bf8380016fdf (patch)
tree31545d7ff23e099fb3a25e600b151820bb63754f /src/drivers/uart/uart8250mem.c
parent3a2d4000cefe2f054a4ad53f95e06e6cbc86b5fc (diff)
mb/google/reef: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms. This is done by adding missing pads to the bootblock gpio table. The soc code gets dropped in CB:49410. Change-Id: I95993b1bd4f1fd8b4ac7b21fb89ec4d196b0240a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49412 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/uart/uart8250mem.c')
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