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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-12 01:38:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 12:10:14 +0000 |
| commit | da44e34743a758aaf9cfa3eac5cf1278297e27e4 (patch) | |
| tree | aad2025b31c7d0fa0c6cfe2dff4d8c9c69780dd5 /src/drivers/spi/acpi/chip.h | |
| parent | 786a1fec27824632dc441582b5edb2cf9305a1b5 (diff) | |
nb/intel/pineview: Select 1M TSEG
With the only valid GTT setting being 1M, TSEG_BASE can only be
aligned to TSEG_SIZE if it is also 1M. This alignment requirement
comes from the desire to use SMRR to protect the SMM RAM.
Tested on Foxconn D41S.
Change-Id: Ibd879529923a1676f2e78500797a52d8a37b8eef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/spi/acpi/chip.h')
0 files changed, 0 insertions, 0 deletions