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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-06-14 14:57:54 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-06-21 15:47:31 +0000
commit35282a0f1b059a42a5a2abef03b559a719cd230f (patch)
tree9bc8d64627f266541f7d5062145e3f86c3279705 /src/drivers/spi/Makefile.inc
parentcd7dfaf3b03a972dedb5f04b33719fd5c6042f51 (diff)
soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem
PM registers used for generating SWS values are being stored in a static variable within southbridge.c. In order to have it available for any source involved in building the platform, move the storage to cbmem, using id CBMEM_ID_POWER_STATE. Also add a variable that informs from which state the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This variable will later be useful in detecting failed S3 resume. BUG=b:80119811 TEST=Add code to print SWS parameters and state it's waking from. Build and boot grunt, suspend and resume, check output for valid values. Remove the print code. Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27109 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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