diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-13 17:36:39 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-14 23:06:21 +0100 |
| commit | c253a92299d832a39af4bed1818255ab61674d10 (patch) | |
| tree | 62012ae33fb4d708278d138e378326d276a5a75e /src/drivers/intel | |
| parent | 98e77c77fd711987f551834b90c5316727ea059a (diff) | |
drivers/intel/fsp1_1: Only display MMCONF address if supported
Disable the display of the MMCONF_BASE_ADDRESS if it is not supported.
TEST=Build and run on Galileo Gen2
Change-Id: Ie4f0fbf264662b5bc12ca923f25395e5e91defea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18801
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 73fb66dee6..3933b2e193 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -60,8 +60,9 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) memset(&pei_data, 0, sizeof(pei_data)); /* Display parameters */ - printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", - CONFIG_MMCONF_BASE_ADDRESS); + if (!IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using FSP 1.1\n"); /* Display FSP banner */ |