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authorElyes HAOUAS <ehaouas@noos.fr>2019-07-11 09:22:02 +0200
committerMartin Roth <martinroth@google.com>2019-07-15 02:26:52 +0000
commitb56224408ef6ff152ba1544ea6c38cad26576c97 (patch)
treea3c3d7c6a6c7f9322f18726fe40b608c23042494 /src/drivers/intel
parent9fe5dde68d8f07a1f78785f48fc39e6acdc98e6b (diff)
src: Use '#include <timestamp.h>' when needed
Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp1_1/car.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 1e89a8eb89..19eb041eac 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -23,7 +23,6 @@
#include <fsp/util.h>
#include <fsp/memmap.h>
#include <program_loading.h>
-#include <timestamp.h>
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,