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authorAndrey Petrov <andrey.petrov@intel.com>2016-03-17 16:42:41 -0700
committerAaron Durbin <adurbin@chromium.org>2016-04-08 00:33:55 +0200
commita6dd53535410f552809501d613de127a7b4b8d90 (patch)
treeb704ab5e7c1c0a4a3fbb570d08a0970ae0d0c514 /src/drivers/intel
parentb0801e11f0f0d46191464cce3dfa1ab2af438cc6 (diff)
drivers/intel/fsp2_0: Add boot mode constants
This adds boot mode constants. They match EDK2 found in PiBootMode.h constants but are part of FSP2.0 spec. Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/api.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index c098a5b143..d49fc42c42 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -35,6 +35,16 @@ enum fsp_status {
FSP_CRC_ERROR = 0x8000001b,
};
+enum fsp_boot_mode {
+ FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00,
+ FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01,
+ FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02,
+ FSP_BOOT_ON_S4_RESUME = 0x05,
+ FSP_BOOT_ON_S3_RESUME = 0x11,
+ FSP_BOOT_ON_FLASH_UPDATE = 0x12,
+ FSP_BOOT_IN_RECOVERY_MODE = 0x20
+};
+
enum fsp_notify_phase {
AFTER_PCI_ENUM = 0x20,
READY_TO_BOOT = 0x40