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authorSubrata Banik <subrata.banik@intel.com>2021-05-28 02:26:31 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-05-29 06:09:04 +0000
commitde77449c3946e89140fe53ca636d77a23ccc503c (patch)
tree36d04155709112e20707cc0ed349394d88c69f30 /src/drivers/intel
parent83e0b97dc567c145bff21cd8a816b92924d09092 (diff)
drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static
fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp2_0/include/fsp/api.h1
-rw-r--r--src/drivers/intel/fsp2_0/temp_ram_exit.c2
2 files changed, 1 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 8561600714..a095b78b5f 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -34,7 +34,6 @@ enum fsp_notify_phase {
/* Main FSP stages */
void fsp_memory_init(bool s3wake);
void fsp_silicon_init(void);
-void fsp_temp_ram_exit(void);
/*
* Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S
diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c
index 0ef6c5cc78..5d7cbd4ebb 100644
--- a/src/drivers/intel/fsp2_0/temp_ram_exit.c
+++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c
@@ -7,7 +7,7 @@
#include <cbfs.h>
#include <types.h>
-void fsp_temp_ram_exit(void)
+static void fsp_temp_ram_exit(void)
{
struct fsp_header hdr;
uint32_t status;