From de77449c3946e89140fe53ca636d77a23ccc503c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 28 May 2021 02:26:31 +0530 Subject: drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/intel/fsp2_0/include/fsp/api.h | 1 - src/drivers/intel/fsp2_0/temp_ram_exit.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/drivers/intel') diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 8561600714..a095b78b5f 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -34,7 +34,6 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); -void fsp_temp_ram_exit(void); /* * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 0ef6c5cc78..5d7cbd4ebb 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -7,7 +7,7 @@ #include #include -void fsp_temp_ram_exit(void) +static void fsp_temp_ram_exit(void) { struct fsp_header hdr; uint32_t status; -- cgit v1.2.3