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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-02-11 01:17:01 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-14 11:16:27 +0000 |
| commit | 681ef51d731617a0a4d5b604d561acdecb9c9cfa (patch) | |
| tree | ba6a848963f848960e7a6eb8b947af30e2236e57 /src/drivers/intel/gma/opregion.h | |
| parent | 3ab36b84f721009e14c230c370bd90e05d47856c (diff) | |
drivers/intel/gma: fix opregion SCI register for Atom platforms
Most Intel platforms use separate registers for software-based
SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single
combined register (0xe0) for both. Adjust opregion implementation
to use the correct register for Atom-based platforms.
Test: Boot Windows on Atom-based ChromeOS device with Tianocore
payload and non-VBIOS graphics init; observe Intel display
driver loaded correctly and internal display not blank.
(requires additional change for Atom platforms to select
CONFIG_INTEL_GMA_SWSMISCI)
Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/drivers/intel/gma/opregion.h')
| -rw-r--r-- | src/drivers/intel/gma/opregion.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 3ae68e527b..8ef3dcf9be 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -25,6 +25,7 @@ /* IGD PCI Configuration register */ #define ASLS 0xfc /* OpRegion Base */ #define SWSCI 0xe8 /* SWSCI Register */ +#define SWSMISCI 0xe0 /* SWSMISCI Register */ #define GSSCIE (1 << 0) /* SCI Event trigger */ #define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ |