diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:51:08 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 15:51:52 +0000 |
| commit | d161a2fafd14700b133b1deca7b8a9a5ca1c5283 (patch) | |
| tree | cf091c2582e17442eb5096322b3c0f328cdbffa0 /src/drivers/intel/gma/i915_reg.h | |
| parent | 490546f191cf2aa1aceec97b7d0503f4fb4408f4 (diff) | |
src/drivers: Drop unneeded empty lines
Change-Id: I202e5d285612b9bf237b588ea3c006187623fdc3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/drivers/intel/gma/i915_reg.h')
| -rw-r--r-- | src/drivers/intel/gma/i915_reg.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 0f3b3d0e49..137d7673fb 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -27,7 +27,6 @@ #define IVB_GMCH_GMS_SHIFT 4 #define IVB_GMCH_GMS_MASK 0xf - /* PCI config space */ #define HPLLCC 0xc0 /* 855 only */ @@ -296,7 +295,6 @@ #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ - /* * Reset registers */ @@ -791,7 +789,6 @@ #define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21) - /* * Framebuffer compression for Sandybridge * @@ -801,7 +798,6 @@ #define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104 - /* * GPIO regs */ @@ -1213,7 +1209,6 @@ HSW_CXT_RENDER_SIZE(ctx_reg) + \ GEN7_CXT_VFSTATE_SIZE(ctx_reg)) - /* * Overlay regs */ @@ -1254,7 +1249,6 @@ #define _BCLRPAT_B 0x61020 #define _VSYNCSHIFT_B 0x61028 - #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) @@ -1311,7 +1305,6 @@ #define ADPA_DPMS_STANDBY (2<<10) #define ADPA_DPMS_OFF (3<<10) - /* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 #define HDMIB_HOTPLUG_INT_EN (1 << 29) @@ -2808,7 +2801,6 @@ #define _PIPEB_FRMCOUNT_GM45 0x71040 #define _PIPEB_FLIPCOUNT_GM45 0x71044 - /* Display B control */ #define _DSPBCNTR 0x71180 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) @@ -3011,7 +3003,6 @@ #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff - #define _PIPEA_DATA_M1 0x60030 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ #define TU_SIZE_MASK 0x7e000000 @@ -3565,7 +3556,6 @@ #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) #define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31) - #define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 #define FDIA_PHASE_SYNC_SHIFT_EN 18 |