diff options
| author | Martin Roth <gaumless@gmail.com> | 2023-09-03 21:38:29 -0600 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-09-08 00:53:57 +0000 |
| commit | 74f18777a2e6919172a4214c3195bfcc48f48407 (patch) | |
| tree | 792af40f72ed0f4287239a707acce3edbe89c9d2 /src/drivers/intel/gma/i915_reg.h | |
| parent | cef239675b46ffec6c3c4a99875329f0ee92a6b5 (diff) | |
arch to drivers/intel: Fix misspellings & capitalization issues
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/gma/i915_reg.h')
| -rw-r--r-- | src/drivers/intel/gma/i915_reg.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 377f903292..8a7ccf77fd 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -15,7 +15,7 @@ * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory. * This is all handled in the intel-gtt.ko module. i915.ko only - * cares about the vga bit for the vga rbiter. + * cares about the vga bit for the vga arbiter. */ #define INTEL_GMCH_CTRL 0x52 #define INTEL_GMCH_VGA_DISABLE (1 << 1) @@ -1384,7 +1384,7 @@ #define SDVOC_GANG_MODE (1 << 16) #define SDVO_ENCODING_SDVO (0x0 << 10) #define SDVO_ENCODING_HDMI (0x2 << 10) -/** Requird for HDMI operation */ +/** Required for HDMI operation */ #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) #define SDVO_COLOR_RANGE_16_235 (1 << 8) #define SDVO_BORDER_ENABLE (1 << 7) @@ -1485,7 +1485,7 @@ /* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 -/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC +/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte * of the infoframe structure specified by CEA-861. */ #define VIDEO_DIP_DATA_SIZE 32 @@ -1630,7 +1630,7 @@ #define BLC_HIST_CTL 0x61260 /* New registers for PCH-split platforms. Safe where new bits show up, the - * register layout machtes with gen4 BLC_PWM_CTL[12]. */ + * register layout matches with gen4 BLC_PWM_CTL[12]. */ #define BLC_PWM_CPU_CTL2 0x48250 #define BLC_PWM2_ENABLE (1UL<<31) #define BLC_PWM_CPU_CTL 0x48254 @@ -2037,7 +2037,7 @@ /** Sets the rollover for the second subcarrier phase generation DDA */ # define TV_SCDDA2_SIZE_MASK 0x7fff0000 # define TV_SCDDA2_SIZE_SHIFT 16 -/** Sets the increent of the second subcarrier phase generation DDA */ +/** Sets the increment of the second subcarrier phase generation DDA */ # define TV_SCDDA2_INC_MASK 0x00007fff # define TV_SCDDA2_INC_SHIFT 0 @@ -2045,7 +2045,7 @@ /** Sets the rollover for the third subcarrier phase generation DDA */ # define TV_SCDDA3_SIZE_MASK 0x7fff0000 # define TV_SCDDA3_SIZE_SHIFT 16 -/** Sets the increent of the third subcarrier phase generation DDA */ +/** Sets the increment of the third subcarrier phase generation DDA */ # define TV_SCDDA3_INC_MASK 0x00007fff # define TV_SCDDA3_INC_SHIFT 0 |