diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2022-12-01 15:45:51 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-01-11 13:59:54 +0000 |
| commit | 765e5df0dddbb12927dbcc8a8315ed4c99357984 (patch) | |
| tree | 571327fd8ebbcb5aec26981ef01848cb97a29883 /src/drivers/intel/gma/Kconfig | |
| parent | ea2dbdba2e5a27d47fb3b7834951cff2e0f40628 (diff) | |
drivers/intel/gma: Hook up libgfxinit in romstage
A mainboard port needs to:
- select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT'
- implement the Ada package `GMA.Mainboard' with a single function
`ports' that returns a list of ports to be probed for displays.
- set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use
in romstage (and ramstage) for the graphic device.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libgfxinit compiles in romstage.
libgfxinit successfully executes in romstage and ramstage using
the requested MMIO setting on skolas.
Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/gma/Kconfig')
| -rw-r--r-- | src/drivers/intel/gma/Kconfig | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 87f6d125d2..8aed404f78 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -90,15 +90,31 @@ config GFX_GMA depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE +config EARLY_GFX_GMA + def_bool y + depends on SOC_INTEL_ALDERLAKE + depends on MAINBOARD_USE_EARLY_LIBGFXINIT + select ROMSTAGE_LIBHWBASE + +config GFX_GMA_DEFAULT_MMIO + hex + depends on HWBASE_STATIC_MMIO && (GFX_GMA || EARLY_GFX_GMA) + help + Graphics device MMIO address. This is typically an unused + memory mapping region which can be allocated to the MMIO + region as graphics PCI device Base Address Range zero. + config GFX_GMA_PANEL_1_ON_EDP bool - depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ + || MAINBOARD_HAS_EARLY_LIBGFXINIT default n if GFX_GMA_PANEL_1_ON_LVDS default y config GFX_GMA_PANEL_1_ON_LVDS bool - depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ + || MAINBOARD_HAS_EARLY_LIBGFXINIT default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE default n @@ -111,7 +127,7 @@ config INTEL_GMA_OPREGION_2_1 bool default n -if GFX_GMA +if GFX_GMA || EARLY_GFX_GMA config GFX_GMA_DYN_CPU def_bool y |