diff options
author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2016-08-24 16:05:32 +0530 |
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committer | Martin Roth <martinroth@google.com> | 2016-08-31 17:39:05 +0200 |
commit | 4dfe13081922454e97e6b0f8d6532cd97c635b60 (patch) | |
tree | 6de04389a077cddbff70e76d2605e68246985ad4 /src/drivers/intel/fsp2_0/stage_cache.c | |
parent | 3156934bf8f059fb8ba14965b75ed0ccb56c79cb (diff) |
driver/intel/fsp2.0: Add External stage cache region helper
If ramstage caching outside CBMEM is enabled
i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a
helper function to determine the caching region in SMM
should be implemented. Add the same to FSP2.0 driver.
FSP1.1 driver had the same implementation hence copied stage_cache.c.
The SoC code should implement the smm_subregion to provide
the base and size of the caching region within SMM. The fsp/memmap.h
provides the prototype and we will reuse the same from FPS 1.1.
Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16312
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/intel/fsp2_0/stage_cache.c')
-rw-r--r-- | src/drivers/intel/fsp2_0/stage_cache.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c new file mode 100644 index 0000000000..2d594e6048 --- /dev/null +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/memmap.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} |