drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support

Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):

1. It supports FSP-M multi-phase init. Some fields have been added to
   the FSP header data structure for this purpose.

2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
   used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.

3. It support 64-bits FSP but 64-bits support will be provided by
   subsequent patch.

Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase.

[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf

[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf

TEST=verified on Lunar Lake RVP board (lnlrvp)

Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>

3 files changed, 17 insertions, 1 deletions

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 40a64e68c8..971be0d207 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -48,6 +48,7 @@ void fsps_load(void);
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
 /* Callbacks for SoC/Mainboard specific overrides */
+void platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index);
 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index);
 /* Check if MultiPhase Si Init is enabled */
 bool fsp_is_multi_phase_init_enabled(void);
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index fceebec7ed..f495822e19 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -37,6 +37,8 @@ struct fsp_header {
 	uint32_t  fsp_multi_phase_si_init_entry_offset;
 	uint16_t  extended_image_revision;
 	uint16_t  res4;
+	uint32_t  fsp_multi_phase_mem_init_entry_offset;
+	uint32_t  res5;
 }  __packed;
 #else
 #error You need to implement this struct for x86_64 FSP
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index acf337f661..bed4fcb29e 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -16,6 +16,14 @@
 
 #define FSP_VER_LEN	30
 
+#if CONFIG(PLATFORM_USES_FSP2_4)
+#define FSPM_ARCHx_UPD FSPM_ARCH2_UPD
+#define FSPS_ARCHx_UPD FSPS_ARCH2_UPD
+#else
+#define FSPM_ARCHx_UPD FSPM_ARCH_UPD
+#define FSPS_ARCHx_UPD FSPS_ARCH_UPD
+#endif
+
 /* Macro for checking and loading array type configs into array type UPDs */
 #define FSP_ARRAY_LOAD(dst, src) \
 do { \
@@ -48,6 +56,11 @@ struct fsp_multi_phase_params {
 	void *multi_phase_param_ptr;
 };
 
+struct fsp_multi_phase_get_number_of_phases_params {
+	uint32_t number_of_phases;
+	uint32_t phases_executed;
+};
+
 struct hob_resource {
 	uint8_t owner_guid[16];
 	uint32_t type;
@@ -198,7 +211,7 @@ typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param);
 typedef asmlinkage uint32_t (*fsp_memory_init_fn)
 				   (void *raminit_upd, void **hob_list);
 typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd);
-typedef asmlinkage uint32_t (*fsp_multi_phase_si_init_fn)(struct fsp_multi_phase_params *);
+typedef asmlinkage uint32_t (*fsp_multi_phase_init_fn)(struct fsp_multi_phase_params *);
 typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *);
 #include <fsp/debug.h>