diff options
| author | Julian Schroeder <julianmarcusschroeder@gmail.com> | 2021-11-02 16:32:28 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-02 21:42:34 +0000 |
| commit | 8a576f60ffa0f5d0599033304e6e7e34ea9c8ef6 (patch) | |
| tree | 2699b4fcfd284cee04c02b965e4cad05af59ebe7 /src/drivers/intel/fsp2_0/include/fsp | |
| parent | 7edf910d79cfefb45d4e8e0c770007c8663bb991 (diff) | |
drivers/intel/fsp2_0/include/fsp: fix fsp_header
This patch aligns fsp_header with the Intel specification 2.0 and 2.3.
The main impetus for this change is to make the fsp_info_header fully
accessible in soc/vendor code. Here items such as image_revision can be
checked.
TEST=verify image revision output in the coreboot serial log.
compare to FSP version shown in serial debug output.
verify Google Guybrush machine boots into OS.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp2_0/include/fsp')
| -rw-r--r-- | src/drivers/intel/fsp2_0/include/fsp/info_header.h | 43 |
1 files changed, 25 insertions, 18 deletions
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 136fc2b7a3..fceebec7ed 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -10,27 +10,34 @@ #define FSP_HDR_ATTRIB_FSPT 1 #define FSP_HDR_ATTRIB_FSPM 2 #define FSP_HDR_ATTRIB_FSPS 3 +#define FSP_IMAGE_ID_LENGTH 8 #if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { - uint32_t fsp_revision; - uint16_t extended_fsp_revision; - uint32_t image_size; - uint32_t image_base; - uint16_t image_attribute; - uint8_t spec_version; - uint16_t component_attribute; - uint32_t cfg_region_offset; - uint32_t cfg_region_size; - uint32_t temp_ram_init_entry; - uint32_t temp_ram_exit_entry; - uint32_t notify_phase_entry_offset; - uint32_t memory_init_entry_offset; - uint32_t silicon_init_entry_offset; - uint32_t multi_phase_si_init_entry_offset; - char image_id[sizeof(uint64_t) + 1]; - uint8_t revision; -} __packed; + uint32_t signature; //FSPH + uint32_t header_length; + uint8_t res1[2]; + uint8_t spec_version; + uint8_t header_revision; + uint32_t image_revision; + char image_id[FSP_IMAGE_ID_LENGTH]; // not zero terminated + uint32_t image_size; + uint32_t image_base; + uint16_t image_attribute; + uint16_t component_attribute; + uint32_t cfg_region_offset; + uint32_t cfg_region_size; + uint32_t res2; + uint32_t temp_ram_init_entry_offset; //initial stack + uint32_t res3; + uint32_t notify_phase_entry_offset; + uint32_t fsp_memory_init_entry_offset; + uint32_t temp_ram_exit_entry_offset; + uint32_t fsp_silicon_init_entry_offset; + uint32_t fsp_multi_phase_si_init_entry_offset; + uint16_t extended_image_revision; + uint16_t res4; +} __packed; #else #error You need to implement this struct for x86_64 FSP #endif |