Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"

This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was
originally introduced as a workaround for the bug that the Linux kernel
doesn't know what to do with type 16 memory region in the e820 table
where CBMEM resides and disallowed accessing it. After depthcharge was
patched to mark the type 16 region as a normal reserved region, the
Linux kernel now can access the BERT region and print BERT errors. When
SeaBIOS was used as payload it already marked the memory region
correctly, so it already worked in that case.

After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the
usage of the BERT memory region reserved by the FSP driver by the AMD
Picasso and Cezanne SoCs and made them use CBMEM for the BERT region,
no other SoC code uses this functionality. The Intel Alderlake and
Tigerlake SoCs put the BERT region in CBMEM and never used this reserved
memory region and the change for the Intel server CPU to use this was
abandoned and never landed in upstream coreboot. AMD Stoneyridge is the
only other SoC/chipset that selects ACPI_BERT, but since it doesn't
select or use the FSP driver, it also won't be affected by this change.

TEST=Behavior of the BERT code doesn't change on Mandolin

Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 8 deletions

diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c
index 5388b8912a..0efb462b40 100644
--- a/src/drivers/intel/fsp2_0/cbmem.c
+++ b/src/drivers/intel/fsp2_0/cbmem.c
@@ -6,14 +6,7 @@
 void *cbmem_top_chipset(void)
 {
 	struct range_entry tolum;
-	uint8_t *tolum_base;
 
 	fsp_find_bootloader_tolum(&tolum);
-	tolum_base = (uint8_t *)(uintptr_t)range_entry_base(&tolum);
-
-	/*
-	 * The TOLUM range may have other memory regions (such as APEI
-	 * BERT region on top of CBMEM (IMD root and IMD small) region.
-	 */
-	return tolum_base + cbmem_overhead_size();
+	return (void *)(uintptr_t)range_entry_end(&tolum);
 }