diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-07 23:57:48 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-11-10 18:10:54 +0100 |
| commit | 2db5bacd909dbf2d9e9e1e8998b0855ba424145c (patch) | |
| tree | c720e026068b501a95796149b5af36b40ed824f9 /src/drivers/intel/fsp2_0/Kconfig | |
| parent | b038f41420c47d91cc9919930242f9d38696a0a0 (diff) | |
drivers/intel/fsp2_0: Add support for recovery MRC hash space in TPM
This space is read/updated only in recovery mode.
1. During read phase, verify if the hash of MRC data read from
RECOVERY_MRC_CACHE matches the hash stored in TPM.
2. During update phase, calculate hash of training data returned by MRC
and save it in TPM.
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Verified MRC data hash comparison and update operation on reef.
Change-Id: Ifcbbf1bd22033767625ec55b659e05fa7a7afc16
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp2_0/Kconfig')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index c653148696..4f40c3fa25 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -94,4 +94,10 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n +config FSP2_0_USES_TPM_MRC_HASH + bool + default y if HAS_RECOVERY_MRC_CACHE + default n + select VBOOT_HAS_REC_HASH_SPACE + endif |