diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2024-02-18 11:45:30 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2024-03-05 21:26:39 +0000 |
| commit | 0201d989f20b3157d52fb9dca01256ebe6550126 (patch) | |
| tree | b7747a88f5aa0706037b49716247d8ef4896bb63 /src/drivers/intel/fsp2_0/Kconfig | |
| parent | 67166a7eb231dcb3cff5c5b8b407cebcfe6f753f (diff) | |
drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the FSP heap is right above the
RC heap, where both of them are located at the bottom part of CAR.
Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/drivers/intel/fsp2_0/Kconfig')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index e27249ff3c..274c3e5f24 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -221,6 +221,17 @@ config FSP_USES_CB_STACK without reinitializing stack pointer. This feature is supported Icelake onwards. +config FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND + bool + help + Starting with Intel CPX there is a bug in there reference code during + the pipe init. This code synchronises the CAR between sockets in FSP-M. + This code implicitly assumes that the FSP heap is right above the + RC heap, where both of them are located at the bottom part of CAR. + Select this to have an explicit handling of the FSP StackBase to work + around this issue. This is needed on multi-socket Xeon-SP systems. + This will place the FSP heap right above the FSP-M RC heap. + config FSP_TEMP_RAM_SIZE hex help |