summaryrefslogtreecommitdiff
path: root/src/drivers/intel/fsp1_1
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2016-03-07 13:21:56 -0800
committerPatrick Georgi <pgeorgi@google.com>2016-03-14 10:53:19 +0100
commit59be62480e2b9f51a66b5da3d552ae47425db9c6 (patch)
tree7e3eaf7e35540e03d28ac2f92bdad7bd5f69bc16 /src/drivers/intel/fsp1_1
parentbc5ad1087b571f22181f7d3edc91354c03269fbf (diff)
intel/fsp1.1: Mark graphics init done after SiliconInit phase
If the VBT was provided to the FSP GOP driver then graphics init will be done as part of SiliconInit step and we can mark that when it is completed. This will result in the "oprom" flag being set properly in the coreboot gpio table and the netboot firmware will have video. [pg: avoided conflict with Quark that comes without silicon_init_params.GraphicsConfigPtr] BUG=chrome-os-partner:50864 BRANCH=glados TEST=boot image.net.bin on chell and get working graphics without being setuck in a reboot loop thinking graphics needs to be started when it already has been. Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240) Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5 Original-Reviewed-on: https://chromium-review.googlesource.com/331355 Reviewed-on: https://review.coreboot.org/13986 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
-rw-r--r--src/drivers/intel/fsp1_1/ramstage.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 277b60990c..834f148071 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <bootmode.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <cbfs.h>
@@ -140,6 +141,14 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
+ /* Mark graphics init done after SiliconInit if VBT was provided */
+#if IS_ENABLED(CONFIG_GOP_SUPPORT)
+ /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
+ * to be #if'd out instead of using if(). */
+ if (silicon_init_params.GraphicsConfigPtr)
+ gfx_set_init_done(1);
+#endif
+
display_hob_info(fsp_info_header);
soc_after_silicon_init();
}