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authorSubrata Banik <subrata.banik@intel.com>2017-03-07 14:02:23 +0530
committerMartin Roth <martinroth@google.com>2017-03-28 16:38:42 +0200
commit03e971cd23e96b9293fc3ecc420f56ad91326cd9 (patch)
tree722243549211ec6204f190f1d2c1d825d41aa466 /src/drivers/intel/fsp1_1
parent0637e567e13adab5b204a33fc57a54f437761f3f (diff)
soc/intel/common/block: Add cache as ram init and teardown code
Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
-rw-r--r--src/drivers/intel/fsp1_1/after_raminit.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
index 3a4116a5af..cd56ea8dc3 100644
--- a/src/drivers/intel/fsp1_1/after_raminit.S
+++ b/src/drivers/intel/fsp1_1/after_raminit.S
@@ -32,8 +32,8 @@
#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
- /* SOC specific NEM */
- #include <soc/car_teardown.S>
+ /* chipset_teardown_car() is expected to disable cache-as-ram. */
+ call chipset_teardown_car
#else
.extern fih_car