From 03e971cd23e96b9293fc3ecc420f56ad91326cd9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 7 Mar 2017 14:02:23 +0530 Subject: soc/intel/common/block: Add cache as ram init and teardown code Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/drivers/intel/fsp1_1/after_raminit.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/drivers/intel/fsp1_1') diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index 3a4116a5af..cd56ea8dc3 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -32,8 +32,8 @@ #if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - /* SOC specific NEM */ - #include + /* chipset_teardown_car() is expected to disable cache-as-ram. */ + call chipset_teardown_car #else .extern fih_car -- cgit v1.2.3