diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2018-10-01 19:17:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:32 +0000 |
| commit | f677d17ab3cfd1471c0f238a0d32b0d56dd8d37f (patch) | |
| tree | 9b0c01512de536210262110ac4e7dfb78d6849c1 /src/drivers/intel/fsp1_1/romstage.c | |
| parent | 45022ae056cdbf58429b77daf2da176306312801 (diff) | |
intel: Use CF9 reset (part 2)
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/romstage.c')
| -rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 8e8c24c96c..e1910e6ad5 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -22,6 +22,7 @@ #include <assert.h> #include <console/console.h> #include <cbmem.h> +#include <cf9_reset.h> #include <cpu/intel/microcode.h> #include <cpu/x86/mtrr.h> #include <ec/google/chromeec/ec.h> @@ -29,7 +30,6 @@ #include <elog.h> #include <fsp/romstage.h> #include <mrc_cache.h> -#include <reset.h> #include <program_loading.h> #include <romstage_handoff.h> #include <smbios.h> @@ -134,7 +134,8 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); - hard_reset(); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); } @@ -164,7 +165,8 @@ void romstage_common(struct romstage_params *params) /* Create romstage handof information */ if (romstage_handoff_init( params->power_state->prev_sleep_state == ACPI_S3) < 0) - hard_reset(); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); } void after_cache_as_ram_stage(void) |