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authorArthur Heymans <arthur@aheymans.xyz>2019-01-06 07:35:11 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-21 17:37:32 +0000
commitbe291e8abf173e4f12e6d9e5532fdf1acbcb9a67 (patch)
tree12b2a0c6bcf03649b81ef38aa033b5bc06f4a7c0 /src/drivers/intel/fsp1_1/romstage.c
parentf91344cd07a4e9a4c2e183f00431b4fee05daf33 (diff)
soc/intel/fsp1.1: Implement postcar stage
This moves FSP1.1 to use postcar stage to tear down CAR. On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found during the postcar stage so there is no need to push to save it in CAR global variables. On FSP1.1 platforms with an open source CAR implementation (Skylake, even though it still runs the FSP-T), the soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR. This also uses common functions to set up the MTRR to use after CAR is torn down. Test: build/boot on google/celes (BSW) and google/chell (SKL) Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/romstage.c')
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c20
1 files changed, 3 insertions, 17 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 433e16cf13..40c598877f 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -38,9 +38,8 @@
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
-asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
+asmlinkage void romstage_main(FSP_INFO_HEADER *fih)
{
- void *top_of_stack;
struct romstage_params params = {
.chipset_context = fih,
};
@@ -72,17 +71,11 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
mainboard_romstage_entry(&params);
soc_after_ram_init(&params);
post_code(0x38);
-
- top_of_stack = setup_stack_and_mtrrs();
-
- printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
- timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
- return top_of_stack;
}
-void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
+void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
{
- return romstage_main(fih);
+ romstage_main(fih);
}
/* Entry from the mainboard. */
@@ -161,13 +154,6 @@ void romstage_common(struct romstage_params *params)
full_reset();
}
-void after_cache_as_ram_stage(void)
-{
- /* Load the ramstage. */
- run_ramstage();
- die("ERROR - Failed to load ramstage!");
-}
-
/* Initialize the power state */
__weak struct chipset_power_state *fill_power_state(void)
{